| Term | Meaning |
|---|---|
| AD9361 | Analog Devices RF transceiver on the board: two receive and two transmit chains, 70 MHz to 6 GHz, 12-bit ADC and DAC. SatLink uses TX1 and RX1 |
| AGC | Automatic gain control. Two exist: the AD9361's own (disabled when a profile sets rx_gain_db) and the PL's digital AGC in front of the matched filter, whose gain is published as agc_gain |
| Apply (a profile) | Validate a profile, translate it to PL register writes, stage them, commit them through the profile sequencer, then tune the AD9361 |
| ASM | Attached Sync Marker, the 32-bit word (0x1ACFFC1D in CCSDS) placed in front of every coded frame so the receiver can find frame boundaries |
axi_ad9361 | Analog Devices' HDL interface core between the FPGA and the AD9361's LVDS data bus |
| Block (DMA block) | The unit the PS and PL exchange: 4096 samples of 32 bits, i.e. 16 384 bytes carrying 4096 useful bytes under le:u8/32 |
| Campaign | An ordered roadmap of scenarios, board actions and gates, with a cursor that survives a reboot. See Campaigns |
| CCSDS | Consultative Committee for Space Data Systems. SatLink implements parts of 131.0-B (sync and channel coding) in the PL and transfer frames (132.0-B, 732.0-B, 732.1-B) in the PS |
| Chain | The emission chain as a whole: AD9361 calibration and tuning, profile, DAC source, ENSM state, loopback switches, TX egress and datapath. See Chain Conditioning |
| Chain target | Where the samples go: pl (PL loopback), device-loopback (the AD9361's internal digital loopback) or air (the antenna port) |
| Channel emulator | The channel_impair block in the PL: frequency offset, attenuation, noise, burst errors and mute, on the PL loopback path only |
| Commit | The profile sequencer swapping shadow registers into the active bank. It only happens while the datapath is idle |
| CSP | CubeSat Space Protocol. SatLink can build CSP packets (4-byte header) for injection and parse them on receive |
| Datapath | The DMA path between satlinkd and the modem: two IIO devices (TX and RX) the daemon must claim ("acquire") before it can transmit or receive |
| DDC / DUC | Digital down-converter (receive) and up-converter (transmit): an NCO mixer plus decimation or interpolation by 1 to 32 |
| Deframer | The PL block that searches for the ASM, delimits frames, undoes the scrambler and hands the bytes to FEC decoding |
| ENSM | The AD9361's Enable State Machine (alert, fdd, …). The transmitter only emits in an emitting state; alert takes RF off |
| EVM | Error vector magnitude, reported by the demodulator. Lower is better |
| Fill / preamble | Symbols the TX chain inserts before a frame that follows silence (preamble) and between frames (inter-frame fill), so the receiver's loops acquire and stay locked |
| Fishball | The Pluto-class development board (fishball7020) SatLink is validated on |
| Framer | The PL block that cuts the transmit byte stream into frames of FRAME_LEN bytes |
| IIO | Linux Industrial I/O, the kernel framework through which the AD9361 and the modem's DMA buffers are driven |
le:u8/32 | The DMA wire format: one useful byte in the low 8 bits of each little-endian 32-bit word |
| LibreSDR / zynqsdr rev5 | The SatLink product PCB |
| LO | Local oscillator: the AD9361's RF carrier synthesiser, one for RX and one for TX |
| Loopback mux | GLOBAL_CTRL[0]: routes the TX chain's output through the channel emulator into the RX chain instead of to the AD9361 |
| NCO | Numerically controlled oscillator; the fine digital frequency shift in the DDC and DUC |
| PL / PS | Programmable Logic (the FPGA fabric) and Processing System (the dual ARM Cortex-A9 running Linux) of the Zynq |
| Profile | A YAML description of a complete radio configuration (satlink.profile/v1). See RF Profiles |
| Profile sequencer | The PL block that validates, waits for a safe point, and commits staged register writes |
| Release id | r<YYYYMMDD>-<hash>[-dirty], derived from the sources of both repositories and the bitstream; burnt into satlinkd |
| RS(255,223) | The CCSDS Reed-Solomon code: 223 message bytes, 32 parity bytes, corrects up to 16 byte errors per codeword |
| Run / report | One execution of a scenario, and the document it produces (satlink.report/v1): events, assertion results, telemetry samples |
| Scenario | A YAML timeline of actions and a set of assertions (satlink.scenario/v1). See Scenarios |
| Scrambler | The CCSDS pseudo-randomiser (x^8+x^7+x^5+x^3+1), applied to the coded stream before the ASM |
| Shadow / active bank | Double-buffered PL registers: writes land in the shadow; the datapath reads the active bank; a commit swaps them. Reads return the active bank |
| Slot framing | Sending one packet per fixed FRAME_LEN-byte slot, with a 2-byte length prefix, so packet boundaries survive the modem |
| sps | Samples per symbol; fixed at 4 in this bitstream |
| Stub | A telemetry sample read while no bitstream answers (all registers zero). Never counts as a measurement |
| Symbol rate ladder | The fixed set of symbol rates the modem can produce: 19 531.25 baud to 2.5 Mbaud |
| UIO | Linux Userspace I/O. The PL's 1 MiB register window is mapped through /dev/uio0 |
| Verified | An assertion result that rests on something the board measured, as opposed to the scenario's own script or a model |
| Watched register | A PL register sampled on every telemetry tick because it is listed in [telemetry] watch_registers; assertable as reg.<name> |
Getting Started
Glossary
The vocabulary used throughout the SatLink documentation.